It is desirable that an analog to digital converter should have a good resolution, but also exhibit good linearity. The resolution of a converter is quoted as the number of bits that it converts. Typically high performance analog to digital converters exhibit 14, 16 or 18 bit resolution. However a user should also pay attention to other performance metrics of the analog to digital converter, such as integral non-linearity, INL, and differential non-linearity, DNL. The differential non-linearity refers to the relative step sizes of each discrete code produced by the analog to digital converter. In an ideal world if a ramped input voltage is supplied to the analog to digital converter then each transition from one digital code to the next should be equally spaced along the analog input ramp. However differential non-linearity errors can result in these transitions becoming non-equally spaced. It can therefore be useful to think of the analog values as being sorted into different digital “bins” and therefore each bin should be the same size.
U.S. Pat. No. 5,010,339 teaches that DNL errors in converters can be greatly decreased, if not removed, by using a dithering technique. In this document a random offset is generated by a bi-polar digital to analog converter and is added in the analog domain to the input signal following its acquisition by a sample and hold circuit. This dithered input value is then sent to an analog to digital converter which converts the voltage obtained by combining the input voltage with the dither voltage. The analog to digital converter outputs a digital word to a further circuit which then subtracts the dither value from the digitised output word in order to produce the final result. The subtraction of the random offset from the conversion result requires additional digital hardware and also results in a delay from the end of the conversion period to when the corrected value, that is the value with the dither offset removed, can be presented. This technique is applicable for use in all types of analog to digital converter.
Adding a dither value to an analog value to be converted and then subtracting the digital equivalent of the dither value from the conversion result reduces DNL errors. The reduction in DNL errors is due to the conversion result being spread out over a number of codes. Steps in the transfer function of the analog to digital converter that would otherwise cause DNL errors at a particular code are “smeared” out over a number of codes.